Two-Stage Opamp with Folded-Cascodes
This is a comprehensive project for the course Analog IC Analysis and Design. The requirement was to design a two-stage MOS operational amplifier with bias circuits under 0.6µm CMOS technology. Also, the final opamp should have a GBW greater than 10MHz, phase margin greater than 60°ree;, slew rate greater than 10V/µs and open-loop gain greater than 60dB under 3V power supply voltage and 10pF load capacitance.