Data-Streaming Image Processing Architecture
As the final project for the course Microcomputer Principles, I presented a novel image processing architecture with an FPGA-based realization and analysis. This architecture was aimed at providing a high-performance, data-streaming oriented and expandable image processing system framework for a wide variety of applications. For human face recognition, traffic detection and many other image processing systems, real time becomes a common requirement. Meanwhile, the input and output data show a characteristic of streaming and quantitativeness. So if we apply specific hardware rather than CPU for some basic image processing, the cost of system resources and time will be significantly reduced.
Based on the above thought, I proposed a hardware based and data-streaming oriented image processing system framework. In this framework, a processing unit was directly attached to the serial pathway between the end-user camera and external storage. Thus, we could consider the whole structure as an additional module transparent to upper software which offered processed image with unchanged transmission rate. In the processing unit, there was a small buffer of a size equal to the dimension of transformation matrix, which would lead to a short delay. I implemented the system on Altera Cyclone II FPGA DE2 Board using verilog language, and utilized TRDB DC2 toolkits to include a 1.3M-pix CMOS camera into the system for simulation and verification. This project won the best project with full marks in the final defense of the course.